The present invention relates to an IC (Integrated Circuit) having a PROM (Programable Read Only Memory) wherein the PROM can be programmed after the IC is assembled with peripheral circuits on a set board, without affecting the peripheral circuits.
Many set boards are provided with an IC having a PROM, wherein necessary data are recorded for customizing, function of each set board according to each user's needs.
FIG. 6 is a block diagram illustrating an example of a conventional set board having a data terminal 17, a clock terminal 18 and a mode setting terminal 19.
Referring to FIG. 6, the conventional set board comprises;
a first peripheral circuit 12 having a serial interface for data-exchanging with outside of the set board through the data terminal 17 according to a clock signal supplied through the clock terminal 18, PA1 a second peripheral circuit 16 connected to the first peripheral circuit 12, PA1 an IC 73 for exchanging data with the second peripheral circuit 16 through I/O (Input/Output) terminals 73e, referring to data prepared in a PRPM provided therein, PA1 a first power supply 74 for driving the first and the second peripheral circuits 12 and 16, and PA1 a second power supply 75 for driving the IC 73. PA1 the PROM 24, PA1 a mode detector 21 for generating a write ready signal and a terminal set signal by detecting the write mode signal supplied through the mode setting terminal 19, PA1 a PROM control circuit 82 for controlling data-write and dataerase of the PROM 24 according to the write ready signal delivered from the mode detector 21, PA1 a serial interface circuit 23 for preparing data to be written in the PROM 24, when controlled with the write ready signal, from data input through the data terminal 17 making use of the clock signal supplied through the clock terminal 18, PA1 a data processing circuit 26 for processing data exchanged with the second peripheral circuit 16 referring to data stored in the PROM 24 when the IC 73 is not controlled in the writing mode, and PA1 terminal setting circuits 85 for setting terminal status of the I/O terminals 73e controlled by the terminal set signal when the IC 73 is controlled in the writing mode. PA1 a mode detector for detecting a write mode signal supplied for controlling the integrated circuit in a writing mode for data-writing into the PROM, PA1 a terminal mode memory for storing data indicating predetermined statuses, each of I/O terminals of the integrated circuit not used in the writing mode being to be set according to each of the predetermined statuses, respectively; PA1 a terminal mode reader for reading out the data stored in the terminal mode memory and generating terminal mode signals in the write mode, logic of each of the terminal mode signals corresponding to each of the predetermined statuses; and PA1 terminal setting circuits, each of the terminal setting circuits controlling each of statuses of the I/O terminals according to logic of corresponding each of the terminal mode signals in the writing mode. PA1 detecting a write mode signal supplied for controlling the integrated circuit in a writing mode for data-writing into the PROM; PA1 reading out data stored in a terminal mode memory, the data indicating predetermined statuses, each of I/O terminals of the integrated circuit not used in the writing mode being to be set to each of the predetermined statuses, respectively; and PA1 controlling each of statuses of the I/O terminals according to a corresponding one of each of the predetermined statuses in the writing mode.
The IC 73 is also connected to the data terminal 17, the clock terminal 18 and the mode setting terminal 19.
When a write mode signal is supplied to the set board through the mode setting terminal 19, the IC 73 is set in a writing mode and controlled to rewrite the PROM according to data supplied through the data terminal 17 and the clock signal supplied through the clock terminal 18.
In FIG. 6, the set board is connected to a PROM writer 11 for writing data in the PROM.
FIG. 7 is a block diagram illustrating a configuration of the IC 73 of FIG. 6, comprising;
When the write ready signal is delivered, the serial interface circuit 23 stands by for receiving data from outside and the PROM control circuit 82 begins to erase data stored in the PROM 24. After data in all address of the PROM 24 are erased, the PROM control circuit 82 begins data-write processes of the PROM 24 with data supplied through the serial interface circuit 23.
In the ordinary operation mode of the IC 73, each status of the I/O terminals 73e varies according to data to be exchanged with the second peripheral circuit 16, and the second peripheral circuit 16 operates according to statuses of the I/O terminals 73e. However, when the IC 73 is controlled in the writing mode, statuses of the I/O terminals 73e vary independent of circuit configuration of the second peripheral circuit 16 and it may be made to operate abnormally, if the I/O terminals 73e are connected directly to the data processing circuit 26 connected to the PROM 24.
For this purpose, the terminal setting circuits 85 are provided, and when the IC 73 is controlled in the writing mode, every status of the I/O terminals 73e is set to an output status, so that the data processing circuit 26 is not affected, and each output logic is forced to remain at logic LOW, for example, independent of operation of the data processing circuit 26.
FIG. 8 is a circuit diagram illustrating an example of the terminal setting circuits 85, having an nMOS transistor 85-1 with its drain connected to corresponding one of the I/O terminals 73e and its source grounded. Gate of the nMOS transistor 85-1 is controlled by the terminal set signal. So, when the terminal set signal is turned to logic HIGH by the mode detector 21 detecting the write mode signal supplied through the mode setting terminal 19, logic of the I/O terminal 73e is fixed to LOW. In the ordinary operation mode, the terminal set signal is left at logic LOW, making the I/O terminal 73e to accord to logic of data to be exchanged.
However, in the IC 73 of the conventional set board of FIG. 6, statuses of the I/O terminals 73e in the writing mode can not be but fixed a priori independent of circuit configuration of the peripheral circuit 16 to be assembled together with the IC 73. So, statuses of the I/O terminals 73e in the writing mode may still cause some effect to the peripheral circuit 16.
Therefore, the first power supply 74 and the second power supply 75 are prepared separately in the conventional set board of FIG. 6, and the first power supply 74 for driving the first and the second peripheral circuits 12 and 16 is controlled to make them inactive when rewriting the PROM 24 in the IC 73.
Preparing two different power supplies needs complicated wiring and a futile space in the set board as well as a troublesome power supply setting accompanying data writing in the PROM.